In the field of semiconductor technology, integrated circuits are usually produced by projection of structure patterns, formed on masks, onto a semiconductor wafer coated in each case repeatedly with a photosensitive resist and a subsequent transferring of the structure pattern into layers respectively arranged underneath the resist. In order to further advance the miniaturization of structure sizes within the structure patterns in semiconductor technology, resolution enhancement techniques (RET) are increasingly being resorted to for the projection. These involve, in addition to illumination methods such as off-axis illumination or structure-specific methods such as optical proximity correction (OPC), primarily innovative mask techniques such as phase masks, for example.
The best resolution results that can be achieved on a semiconductor wafer by an exposure device in a projection are obtained by the type of alternating or chromeless phase mask. Alternating phase masks are particularly suitable for the projection of a dense line-gap pattern formed on such a mask type and having a width ratio of lines to gaps of about 1:1.
However, phase conflicts may occur in the case of the aforementioned types of phase masks. In the case of an exposure, the phase conflicts lead to undesirable, unexposed resist regions in a photosensitive layer arranged on the semiconductor wafer. With the aid of a second or trimming exposure by a further mask, the structure pattern of which is coordinated with that of the first mask, the regions in the photosensitive layer may subsequently be exposed and removed in a downstream development process.
Such a trimming mask is used to eliminate, e.g., the undesirable resist structures produced by phase conflicts by the application of gaplike structures on the trimming mask at precisely those positions which correspond to the positions of the undesirable resist structures on the wafer so that these are first exposed during the projection of the trimming mask. The trimming mask thus brings about the exposure of the same photosensitive layer which has also already been exposed by the aforementioned first mask, for example, an alternating or chromeless phase mask, without the layer having been removed in the meantime.
In this case, it should be noted that the present discussion is based on the use of a positive resist for the photosensitive layer.
Trimming masks are typically embodied as a chrome mask, due to the absence of the stringent requirements made of a structure width to be achieved on the wafer as in the case, for instance, with phase masks. They can be produced cost-effectively and can also be used to produce larger, lithographically less demanding structure elements of a structure pattern to be imaged jointly by both masks, i.e., a lithographic plane, on the wafer.
Since the gaps introduced into the trimming mask, during the projection, are generally to be positioned directly above or at least in the immediate vicinity above the resist structure to be produced on the wafer, an additionally incident radiation is produced by light diffraction at the gap on the trimming mask in an area proximate to the structure element to be transferred on the wafer, which radiation results in an alteration usually a reduction of the intensity gradient at the edge of the structure to be transferred. This gives rise to the disadvantage of a decrease in the size of the lithographic process window for the projection. A lithographic process window is described, for example, by the set of all the pairs of values of exposure parameters such as radiation dose and focus which are used to achieve an imaging of a structure element within a prescribed structure width tolerance on the wafer.
In the case of special arrangements of the structure elements, having, for instance, line widths, mutual distances orientations, etc., this extends even to a situation in which whole parts of structure patterns cannot be imaged sufficiently well. This brings about the exclusion of such arrangements in the design, which, however, leads to considerable limitations even in the creation of the design. This often also results in an enlargement of the circuit area and thus higher fabrication costs on account of the smaller number of product chips on the wafer.